@W: BN132 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance eSRAM_eNVM_access_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance eSRAM_eNVM_access_sb_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance eSRAM_eNVM_access_sb_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance eSRAM_eNVM_access_sb_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance eSRAM_eNVM_access_sb_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance eSRAM_eNVM_access_sb_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance eSRAM_eNVM_access_sb_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance eSRAM_eNVM_access_sb_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[1] (in view view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Register bit HADDR[0] (in view view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] (in view view:work.eSRAM_eNVM_access_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] (in view view:work.eSRAM_eNVM_access_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] (in view view:work.eSRAM_eNVM_access_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] (in view view:work.eSRAM_eNVM_access_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] (in view view:work.eSRAM_eNVM_access_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] (in view view:work.eSRAM_eNVM_access_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance eSRAM_eNVM_access_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[1] because it is equivalent to instance eSRAM_eNVM_access_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance eSRAM_eNVM_access_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[1] because it is equivalent to instance eSRAM_eNVM_access_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT246 :"c:\users\borgaa\desktop\microchip_training\lab_files\igl2_esram_envm_lab\igl2_esram_envm_rw_fabric\component\work\esram_envm_access_sb\ccc_0\esram_envm_access_sb_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock eSRAM_eNVM_access_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net eSRAM_eNVM_access_sb_0.CCC_0.GL0_net.
@W: MT420 |Found inferred clock eSRAM_eNVM_access_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on net eSRAM_eNVM_access_sb_0.FABOSC_0.FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC.
