Project Settings
Project Name | eSRAM_eNVM_access_syn | Device Name | synthesis: Microsemi IGLOO2 : M2GL090TS
Implementation Name | synthesis | Top Module | eSRAM_eNVM_access
Retiming | 0 | Resource Sharing | 1
Fanout Guide | 10000 | Disable I/O Insertion | 0
Disable Sequential Optimizations | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 143 | 79 | 0 | - | 00m:02s | - | 17/02/2020 12:16:13
(premap) | Complete | 53 | 33 | 0 | 0m:01s | 0m:01s | 149MB | 17/02/2020 12:16:16
(fpga_mapper) | Complete | 59 | 20 | 0 | 0m:02s | 0m:03s | 151MB | 17/02/2020 12:16:19
Multi-srs Generator | Complete |  |  |  | 00m:01s |  |  | 17/02/2020 12:16:15
Area Summary
Carry Cells | 63 | Sequential Cells | 339
DSP Blocks (dsp_used) | 0 | I/O Cells | 10
Global Clock Buffers | 2 | RAM1K18 (v_ram) | 1
LUTs (total_luts) | 389 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
eSRAM_eNVM_access_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 131.2 MHz | 2.377
eSRAM_eNVM_access_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA
Optimizations Summary
Combined Clock Conversion | 0 / 1 |  |