#--  Synopsys, Inc.
#--  Version O-2018.09M-SP1-1
#--  Project file C:\Users\borgaa\Desktop\Microchip_training\Lab_files\IGL2_eSRAM_eNVM_lab\IGL2_eSRAM_eNVM_RW_Fabric\synthesis\run_options.txt
#--  Written on Mon Feb 17 12:16:11 2020


#project files
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/hdl/AHB_IF.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/work/TPSRAM_C0/TPSRAM_C0_0/TPSRAM_C0_TPSRAM_C0_0_TPSRAM.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/work/TPSRAM_C0/TPSRAM_C0.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/hdl/eSRAM_eNVM_RW.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/work/eSRAM_eNVM_access_sb/CCC_0/eSRAM_eNVM_access_sb_CCC_0_FCCC.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/work/eSRAM_eNVM_access_sb/FABOSC_0/eSRAM_eNVM_access_sb_FABOSC_0_OSC.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/work/eSRAM_eNVM_access_sb_HPMS/eSRAM_eNVM_access_sb_HPMS_syn.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/work/eSRAM_eNVM_access_sb_HPMS/eSRAM_eNVM_access_sb_HPMS.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/work/eSRAM_eNVM_access_sb/eSRAM_eNVM_access_sb.v"
add_file -verilog "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/component/work/eSRAM_eNVM_access/eSRAM_eNVM_access.v"
add_file -fpga_constraint "C:/Users/borgaa/Desktop/Microchip_training/Lab_files/IGL2_eSRAM_eNVM_lab/IGL2_eSRAM_eNVM_RW_Fabric/designer/eSRAM_eNVM_access/synthesis.fdc"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology IGLOO2
set_option -part M2GL090TS
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "eSRAM_eNVM_access"

# hdl_compiler_options
set_option -distributed_compile 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./eSRAM_eNVM_access.vm"
impl -active "synthesis"
